Given the number of strips to be read (~2000) in the GRIT project, highly integrated electronics is required.
Two ASICs will be used in the project: the iPACI preamplifiers, which give charge and current information and the PLAS analog memory, that sample the signals before sending them to the back-end electronics.
- The iPACI (integrated Charge and Current preamplifier) ASIC is being developed at IPN for the DSSSD readout. It will be fed with the DSSSD outputs and will embed the required hardware to extract the charge, current and time information.
The first version of iPACI, is a 9-channel read-out chip with independent charge and current outputs. The architecture of the chip is shown in Fig.7. It is composed of nine identical channels, each comprising a charge-and-current preamp, and two output buffers. The performance measured on a testbench (without detector and/or alpha source) is summarized in Tab. 1.
|Table 1 : Measured performances of iPACI v1
||1.5V single ended
|Equivalent noise Charge
||[4MHz .. 120MHz]
|Charge output recovery
|Detector’s input capacitance
||Compatible with [10pF .. 40pF] range
||12mA (40mW) / Channel
- A second version of the ASIC, called iPACI v2, has been designed. It is a 16-Channel particle detector read-out chip, which integrates several common functions, i.e. slow shaper, Time-to-Amplitude Converter (TAC), serializer, fast shaper. The ASIC embeds slow control circuitry, enabling real-time tuning. Fig. 8 shows the chip’s architecture.
Keeping the same philosophy as for iPACI v1, the charge and current signals can be selectively sent out. Two ranges in energy are implemented in order to read out thin detector signals for light and heavier particles.
Other features like fast and slow shaper have been implemented in order to be able to read a possible second layer of Silicon. In this case, pulse shape analysis would not be needed as the ΔE-E technique already gives the particle identification. Tab. 2 gives a summary of the simulated performance of iPACI v2.
The University of Valencia (R. Aliaga, V. Herrerro-Bosch) is developing an analog memory ASIC called PLAS (ALI15), for PipeLined Asymmetric SCA for the Silicon array. A novel 32-input analog memory, with self-triggering channels for the sampling of detector’s pulses and their transmission at slower pace. The pipelined asymmetric SCA reduces the number of SCA cells needed by a factor of 7 with respect to single full SCA, thus reducing the size of the chip and power consumption.
||12 bits ENOB
|Nb of entrance channels
||[10pF .. 40pF]
Table 3: Simulated characteristics of PLAS.
Captured signals are timestamped and transmitted serially to the back-end by means of single analog output, reducing considerably the number of feedthroughs. They are digitzed remotely and processed by FPGA (FASTER back-end) that controls read out process at 50 MHz. The 100 MHz sampling clock is handled by the back-end electronics. Both clock edges are used for the sampling to reach 200 MSa/s.